Roll No......................
Total No. Of Questtions:13
Paper ID [ A0210]
BCA (205)(S05)(O)
(Sem.-2nd)
DIGITAL CIRCUITS AND
LOGIC DESIGN
Time : 03 Hrs.
Instruction to Candidates:
1. Section
– A is Compulsory
2. Attempt
any Nine questions from Section – B
Section
– A
1.
a. Convert (i) 11011.11(binary number to decimal number.
(ii)
7825.6875 decimal number to octal.
b. Convert
(i ) 125.89 binary number to BCD
number
(ii)
A4F to octal number.
c. Simplify
(a+b)+(a+b)
d. Prove
using truth table
A+AB=
A+B
e. Draw
the logic diagram & truth table of full adder.
f. Define
the term propagation Delay.
g. Simply
the following logic function using K-map and find the Minterms & maxterms.
F(X,Y,Z)=XZ+XYZ+YZ
h. Write
the truth table of 3-8 Decoder.
i. State
& prove the De- Margin theorems.
j. What
do you mean by race around condition?
k. Explain
the term LOCKOUT with the help of a suitable example?
l. What
is the difference between Latch and a flip flop?
m. What
is a shift register? What are the various configuration of shift register?
n. Differentiate
between synchronous & asynchronous logical circuits.
o. Explain
the operation of master- save flip-flop?
Section
–B
2. What
do you mean by error detecting and correcting codes ? explain both with the
help of suitable examples .
3. Obtain
the truth table of the following & implement it by using NAND Gates?
F(A,B,C,D)=
(AB+BC) (AC+BC)
4. Minimize
the following using K-Map and Realize it with NAND Gates?
F(A,B,C,D)=
∑m(2,3,4,5,13,15)+ ∑d(8,9,10,11)
5. Implement
BCD to Excess -3 Code converter?
6. Explain
the following terms with help of suitable examples.
a. HAZARDS
b. RACES
7. Implement
following using 4X16 Decoder.
F=X
Y +Z
8. What
do you mean by Multiplexer. Draw the block diagram and logical diagram of 4:1
Multiplexer.]
9. Design
a synchronous counter using JK flip flop for the following sequence?
000,101,110,111,011,010,000
10.
Explain the term
universal shift register.
11.
Classify the counters
and discuss the BCD Counters . Also explain Ring
counters
12.
Explain the Various
rules of K-map reduction technique.
13.
Give any five
differences between combinational & sequential logical circuits.
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