Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 2

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B.TECH. 3^RD SEMESTER

EC-205- DIGITAL ELECTORNICS

Time :3 hrs

Note : This paper consists of three sections. Section A is compulsory. Attempt any four questions form section B and two form Section C.

1.                  

a.                 List the advantages of  hexadecimal number system.

b.                 How will you detect overflow in signed-magnitude and Z’s complement integer additions.

c.                  Realize a z –input XOR gate using NAND gates only.

d.                 Simplify(A.B(C+B.D)+ A,B.) C.

e.                  What is meant by CAM ?

f.                   What do you understand by ‘race condition’ in flip-flops?

g.                 How many bits will a D/A converter use so that its full-scale output voltage is 5V and its 

            resolution is at the most 10mv.

h.                 Name the four triggering methods.

i.                   Define ‘propagation delay time’ and ‘figure of merit’

j.                   What are advantages of CMOS logic family over other logic families.

Section –B

2.                 Minimize the function using K-map method and implement the same using NAND/NOR 

            gates. F(A,B,C,D) = TTM (1,2,3,8,9,10,11,14). D(7,15)

3.                 What is a ROM? What are the different types of ROMs? Give the characteristics features of 

           each.

4.                 What is PLA? Design a  BCD to excess- 3 code converter using PLA.

5.                 Draw the circuit of a 3 – input ECL nor gate & discuss its operation what is the primary 

            advantages of ECL gate.

6.                 Devise a method of measuring frequency by means of a counter. Draw the circuit.

Section –C

7.                   

a.                 Convert a given Dflip- flop to a JK flip flop.

b.                 Discuss weighted resistor D/A converter.

8.                   

a.                 Design a synchronous mod – 6counter.

b.                 Realize the expression

           F(a,b,c,d) = Ʃm(0,2,3,6,8,9,12,14) using a 8:1 multiplexer and an inverter

9.              

      

a.                 Design a parity generator to generate an odd parity bit for a 4-bit word(Use minimum number            of gates)

b.                 Define a Register. Construct a shift register form RS flip-flops and explain their operation.