Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 5

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Total No. Of questions: 9]

EC -205

DIGITAL ELECTONICS

(B.Tech. 3^rd Semester , 5001)

Note :- This paper consist of Three SECTIONS. Section A is compulsory.  Do any four questions from section B and any Two question from Section c.

1.                   

a.                 What is Positive Logic and Negative Logic?

b.                 Draw the truth table of al Logic gates.

c.                  Realize an And gate using Nor gates only.

d.                 What is the difference between multiplexer

e.                   Give comparison between various A-D conceders.

f.                   What is Base Current Hogging? How as it eliminated?

g.                 What is a Register? List various methods of loading the data into shift register.

h.                 What is the difference between CAM and RAM

i.                   How race around condition is eliminated in Master-Slave J-K flip-flop?

j.                   Perform the following binary subtraction:

           0101010-11010101.

Section –B

2.                 Draw the truth table of a full Subtractor Circuit. Realize the full Subtractor circuit using NOR            gates only.

3.                 Draw the diagram of parallel Comparator A-D converter and explain its operation.

4.                 Minimize the following Boolean expression using K-Map;

           F (w,x,y,z) = (4,5,8,12,13,14,15)

5.                 What is a content addressable memory? How it helps in locating the data at fast speed?

6.                 Draw the circuit of an ECL gate and explain its operation.

Section –C

7.                 Determine the minimal sum-of –products expression for the following Boolean function:

            M (8,12,13,18,19,21,22,24,25,28,31)+dc (1,2,3,6,7,11).

8.                 Design a Synchronous counter to count in the following sequence using J-K flip-flops :                        15,14,13,12,11,10,9,15. Your design should avoid lock –out condition.

9.                    

a.                 Design a four bit parity checker circuit and realize it.

b.                How many 128 x 8 chips are needed to provide a memory capacity of 2048 bytes?             How many address lines must be used to access 2048 bytes?

c.                  Write a short note on memory organization.